Course Info
Lecture Notes
Labs
Homeworks
Documents
Links
Course Information
Term and
Course Credit: Fall 2005, 3 credit hours
Time and
Place: Lecture: MW 3:55 PM - 5:15 PM, Room 239
Instructor:
Dr. Aleksandar Milenkovic
Email: milenka @ ece . uah . edu
Office: 217-L
Phone: (256) 824 6830
Office Hours: M: 5:15-6:15 PM and W: 12:30-1:30 PM
Lab
Instructor(s): Joel Wilder
Email: wilderj @ ece.uah.edu
Office: EB 242-C
Phone: (256) 824 3484
Office Hours: TR 2:00 - 3:00 PM
Class Web
page: http://www.ece.uah.edu/~milenka/cpe527-05F
Description
The course gives an introduction to digital integrated circuits.
It covers the following topics. CMOS devices and manufacturing
technology. CMOS inverters and gates.
Propagation delay, noise margins, and power dissipation. Sequential
circuits, arithmetic, interconnect, and memories. Design methodologies.
A major part of the course will be a design project.
Text Book
Neil H.E. Weste, David Harris,
CMOS VLSI Design: A Circuits and System Perspective, Addison Wesley,
3e, 2005, ISBN: 0-321-14901-7.
References
J. Rabaey, A. Chandarakasan, B. Nikolic,
Digital Integrated Circuits: A Design Perspective
Prentice Hall, 2/e, ISBN 0-13-090996-3.
Book Web site:
http://bwrc.eecs.berkeley.edu/IcBook/
Prerequisites:
EE 202 Introduction to Digital Logic Design, EE
315 Introduction to Electronic Analysis and Design
Academic
Misconduct
Academic Honesty.
Your written assignments and examinations must be your own work.
Academic Misconduct will not be tolerated. To insure that you are
aware of what is considered academic misconduct, you should review
carefully the definition and examples provided in Article III. Code of
Student Conduct, Student Handbook, p. 93. If you have questions in this
regard, please contact me without delay.
Use of Prior Work.
You may not submit in fulfillment of requirements in this course any
work submitted, presented, or used by you in any other course.
Consent to Use of
Turnitin.com. UAH is committed to the fundamental values
of preserving academic honesty as defined in the Student Handbook
(7.III.A, Code of Student Conduct). The instructor reserves the
right to utilize electronic means to help prevent plagiarism.
Students agree that by taking this course all assignments are subject
to submission for textual similarity review to Turnitin.com.
Assignments submitted to Turnitin.com will be included as source
documents in Turnitin.com’s restricted access database solely for the
purpose of detecting plagiarism in such documents. The terms that
apply to the University’s use of the Turnitin.com service, as well as
additional information about the company, are described at www.
uah.edu/library/turnitin.
Classroom Conduct. All students in the class must treat
others with civility and respect and conduct themselves during class
sessions in a way that does not unreasonably interfere with the
opportunity of other students to learn. Failure to comply with this
requirement may result in points being deducted from a student’s final
numerical average, up to a maximum of 15 points.
Copyright Aleksandar Milenkovic 2005. All federal and
state copyrights in my lectures and course materials are reserved by
me. You are authorized to take notes in class for your own
personal use and for no other purpose. You are not authorized to record
my lectures or to make any commercial use of them or to provide them to
anyone else other than students currently enrolled in this course,
without my prior written permission. In addition to legal
sanctions for violations of copyright law, students found in violation
of these prohibitions may be subject to University disciplinary action
under the Code of student Conduct.
Exam Dates
Test I -
October 12, 2005
Test II –
November 16, 2005
Final Project due –
December 14, 2005 (3:00PM)
Grading
Policy
Final course grades will be determined in the manner outlined below:
Undergraduate students
Components
|
%
of Final Grade
|
Lab Assignment
|
15%
|
Homeworks
|
15%
|
Test I
|
20%
|
Test II
|
20%
|
Project
|
25%
|
Discretion
|
5%
|
Laboratory
Assignments
The lab assignments serve two purposes. First, they allow the
students to apply what is taught during lectures. After
completing all lab assignments the students will have the skills
required to complete the main purpose of the lab – the final
project. During the first semester the students will design and
verify a VLSI circuit using the Mentor Graphics CAD / Cadence tools.
Lecture Notes
Lecture notes will be available in PPT and PDF format.
The notes may be subject to slightly change.
- Week 1 (08/22/05)
- Week 2 (08/29/05)
- Week 3 (09/05/05)
- Labor Day; No classes.
- Session 4 (09/07/05): ppt, pdf(6/1),
pdf(2/1)
[MOS Transistor Theory]
- Week 4 (09/12/05)
- Week 5 (09/19/05)
- Week 6 (09/26/05)
- Session 9 (09/26/05): Meet Joel in lab 246.
- Session 10 (09/28/05): ppt, pdf(6/1),
pdf(2/1) [Logical Effort]
- Week 7 (10/03/05)
- Session 11 (10/03/05): ppt, pdf(6/1), pdf(2/1) [Logical Effort]
- Session 12 (10/05/05): Meet Joel in lab 246.
- Week 8 (10/10/05)
- Session 13 (10/10/05): ppt, pdf(6/1),
pdf(2/1) [Wires]
- Session 14 (10/12/05): ppt, pdf(6/1),
pdf(2/1) [Wires, Desing
for Speed]
- Session 14 (10/12/05); 7:00 PM: Meet AM in EB246 (test
preps).
- Week 9 (10/17/05)
- Session 15 (10/17/05): TEST I
- Session 16 (10/19/05): ppt, pdf(6/1),
pdf(2/1), [Power]
- Week 10 (10/24/05)
- Session 17 (10/24/05): ppt, pdf(6/1),
pdf(2/1) [Design
for Power]
- Session 18 (10/26/05): ppt, pdf(6/1), pdf(2/1) [Circuit styles: Pseudo
nMOS, Domino, Pass
Transistor Logic]
- Week 11 (10/31/05)
- Session 19 (10/31/05): ppt, pdf(6/1), pdf(2/1) [Circuit styles:
Pass
Transistor Logic; Sequential Circuits]
- Session 20 (11/02/05): ppt, pdf(6/1), pdf(2/1) [Sequential Circuits]
- Week 12 (11/07/05)
- Week 13 (11/14/05)
- Week 14 (11/21/05)
- Session 25 (11/21/05): TEST II
- Thanksgiving Holiday: No Classes
- Week 15 (11/28/05)
- Session 26 (11/28/05): Conclusion remarks; pdf(6/1) [Mu0]
- Session 27 (11/30/05): Project Presentations (schedule)
- Week 16 (12/05/05) – Last class
- Session 28 (12/05/05): Project Presentations (schedule)
Laboratory Assignments
Lab hours (…
please sign up for one session)
Lab Session#1: Wednesday 6:00 PM - 7:00 PM
Lab Session#2: Wednesday 7:00 PM - 8:00 PM
Lab Session#3: Wednesday 8:00 PM - 9:00 PM
Labs
Assignments
What
|
Who
|
Issued
|
Due
|
Assignment
|
LAB #1
|
U, G
|
09/02/05
|
09/16/05 (3:00PM, EB242-C)
|
LAB #1
|
LAB #2
|
U, G |
09/09/05 |
09/23/05 (3:00PM, EB242-C)
|
LAB #2
|
LAB #3
|
U, G |
09/21/05 |
10/05/05 (9:00PM, EB242-C)
|
LAB
#3
|
LAB #4
|
U, G |
09/22/05 |
10/14/05 (3:00PM, EB242-C) |
LAB #4
|
LAB #5
|
U, G |
10/04/05 |
10/21/05 (3:00PM, EB242-C) |
LAB
#5
|
LAB #6
|
U, G |
10/14/05
|
10/28/05 (3:00PM, EB242-C) |
LAB
#6
|
Useful
CADENCE tutorials
- Power Analysis using Encounter (.pdf)
- Logical Verification using NCLaunch and Synthesis (VHDL2gates) (.pdf)
Homeworks
What
|
Who
|
Issued
|
Due
|
Assignment
|
HW #1
|
U, G
|
9/15/05
|
9/28/05 (3:55PM)
|
HW #1
|
| HW #2 |
U, G |
10/04/05 |
10/12/05 (3:55 PM)
|
HW #2
|
HW #3 & HW #4
|
U, G |
11/07/05 |
11/16/05 (3:55 PM) |
HW
#3&4 |
|
|
|
|
|
Documents
Links
- MOSIS Scalable CMOS Design Rules
- IC Fabrication
- CADENCE Tutorials
- Useful
- Other