CPE 426/526 - VLSI Using Hardware Description Languages, Modeling, and Synthesis

COURSE INFORMATION:

Credit Hours:

3

Prerequisites:

EE 202, EE 315

Description:

Modern VLSI design techniques and tools, such as silicon compilers

(V)HDL modeling languages, placement and routing tools, synthesis

tools, and simulators. Students will design, simulate, and layout

both programmable logic families and ASIC libraries.

Topics:

• Structured Design Concepts
• Design Tools
• Basic Features of VHDL
• Basic VHDL Modeling Techniques
• Algorithmic Level Design
• Register Level Design
• Gate Level and ASIC Library Modeling
• HDL-Based Design Techniques
• ASICs and the ASIC Design Process
• Modeling for Synthesis
• Integration of VHDL into a Top-Down Design Methodology
• Synthesis Algorithms for Design Automation

Spring 2009 Information

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