entity SHIFTREG is
  port (SI : in BIT;
        CLK : in BIT;
        DATA : inout BIT_VECTOR (7 downto 0));
end SHIFTREG;

architecture BEHAV of SHIFTREG is
begin
  process (CLK)
  begin
    if (CLK'event and CLK = '1') then
      DATA <= SI & DATA (7 downto 1);
    end if;
  end process;
end BEHAV;