CPE 426/526 - VLSI Using Hardware Description Languages, Modeling, and Synthesis

Spring 2009

COURSE INFORMATION:

Credit Hours:

3

Prerequisites:

EE 202, EE 315

Description:

Modern VLSI design techniques and tools, such as silicon compilers

(V)HDL modeling languages, placement and routing tools, synthesis

tools, and simulators. Students will design, simulate, and layout

both programmable logic families and ASIC libraries.

Topics:

• Structured Design Concepts
• Design Tools
• Basic Features of VHDL
• Basic VHDL Modeling Techniques
• Algorithmic Level Design
• Register Level Design
• Gate Level and ASIC Library Modeling
• HDL-Based Design Techniques
• ASICs and the ASIC Design Process
• Modeling for Synthesis
• Integration of VHDL into a Top-Down Design Methodology
• Synthesis Algorithms for Design Automation

Syllabus

Project Presentation Review Form

Project Report Review Form

A Guide to Helpful Unix Terminal Commands

2 Page Verilog Reference

2 Page VHDL Reference

5 Page VHDL Reference

17 Page VHDL Reference

Getting Started with ModelSim

Getting Started with QuestaSim

Getting Started with Design Vision

Getting Started with Quartus (EDF Input)

Getting Started with Quartus (VHDL Input)

Using SDF Files with ModelSim

Lectures

Source for Various Libraries

Book Figures

Helpful VHDL Links

Resource for Project Ideas - particularaly Miscellaneous section

Homework Assignments

Tests and Solutions

CPE 426 Midterm

CPE 426 Midterm Solution

CPE 526 Midterm

CPE 526 Midterm Solution