library ieee;
use ieee.std_logic_1164.all;

entity DLATCH is
  generic (TPDQ, TPGQ : time);
  port (D, G : in std_logic;
        Q, QB : out std_logic);
end DLATCH;

architecture DLATCH of DLATCH is
  signal QTEMP : std_logic;
begin
  process (D, G)
  begin
    if (G'event) then
      if (G = '1') then
        QTEMP <= D after TPGQ;
      end if;
    elsif (D'event) then
      if (G = '1') then
        QTEMP <= D after TPDQ;
      end if;
    end if;
  end process;
  Q <= QTEMP;
  QB <= not QTEMP;
end DLATCH;