entity DLATCH_A is
  port (D, CLK, S, R : in BIT;
        Q, QB : out BIT);
end DLATCH_A;

architecture SYNTH of DLATCH_A is
begin
  process (D, CLK, S, R)
    variable Q_INT : BIT;
  begin
    if (S = '1') then
      Q_INT := '1';
    elsif (R = '1') then
      Q_INT := '0';
    elsif (CLK = '1') then
      Q_INT := D;
    end if;
    QB <= not Q_INT;
    Q <= Q_INT;
  end process;
end SYNTH;