entity MAJ3 is
  generic(DEL: TIME);
  port(X: in BIT_VECTOR(0 to 2); Z: out BIT);
end MAJ3;

architecture DATAFLOW of MAJ3 is
begin
  Z <= (X(0) and X(1)) or (X(1) and X(2))
    or (X(0) and X(2)) after DEL;
end DATAFLOW;
      -- (a) VHDL description

-- Figure 4.16 A majority/consensus element.