use work.SYSTEM_4.all;
entity BUFF_REG is
  generic(STRB_DEL,DAV_DEL,ODEL: TIME);
  port(DI:  in MVL4_VECTOR(7 downto 0);
       STRB,EN: in MVL4;
       DAV: out MVL4;
       DO: out BUS1(7 downto 0):="ZZZZZZZZ");
end BUFF_REG;
--
architecture TWO_PROC of BUFF_REG is
  signal REG: MVL4_VECTOR(7 downto 0);
begin
  FRONT_END: process(STRB,EN)
  begin
    if STRB'EVENT and STRB = '1' then
      REG <=DI after STRB_DEL;
      DAV <= '1' after DAV_DEL;
    end if;
    if EN'EVENT and EN='1' then
      DAV <= '0' after DAV_DEL;
    end if;
  end process FRONT_END;
  --
  OUTPUT: process(REG,EN)
  begin
    if (EN = '1') then
      DO <= DRIVE(REG) after ODEL; else
      DO <= "ZZZZZZZZ" after ODEL;
    end if;
  end process OUTPUT;
end TWO_PROC;
--Figure 5.20 Buffered register model.