entity CLOCK_GENERATOR is
   generic (PER: TIME);
   port(RUN: in BIT;CLK: out BIT);
end CLOCK_GENERATOR;
--
architecture FEEDBACK of CLOCK_GENERATOR is
   signal CLOCK: BIT;
begin
  process (RUN,CLOCK)
    variable CLKE: BIT := '0';
  begin
    if RUN'EVENT then
      if RUN = '1' then
        CLKE := '1';
        CLOCK <= transport '0' after PER/2;
        CLOCK <= transport '1' after PER;
      else
        CLKE := '0';
      end if;
    end if;
    if(CLOCK'EVENT and CLOCK = '1' and CLKE = '1' ) then
      CLOCK <= transport '0' after PER/2;
      CLOCK <= transport '1' after PER;
    end if;
    CLK <= CLOCK;
  end process;
end FEEDBACK;
--Figure 5.14 Algorithmic description of clock generator