entity PAR_TO_SER is
  port(LD,SHCLK: in BIT; PARIN: in BIT_VECTOR(0 to 7);
       BUSY: inout BIT := '0'; SO: out BIT);
end PAR_TO_SER;

architecture TWO_PROC of PAR_TO_SER is
  signal SH_COMP: BIT :='0';
  signal PREG: BIT_VECTOR(0 to 7);
begin
  LOAD:process(LD,SH_COMP)
  begin
    ---- Activities:
    if LD'EVENT and LD='1'and BUSY='0' then
      ----1)Register Load
      PREG <=  PARIN;
      ----2)Busy Set
      BUSY <= '1';
    end if;
      if SH_COMP'EVENT and SH_COMP='1' then
        ----3)Busy Reset
        BUSY <= '0';
      end if;
  end process LOAD;
  SHIFT:process(BUSY,SHCLK)
    variable COUNT: INTEGER;
    variable OREG: BIT_VECTOR(0 to 7);
  begin
    ----Activities:
    if BUSY'EVENT and BUSY = '1' then
      ----1)Shift Initialize
      COUNT := 7;
        OREG := PREG;
      SH_COMP <= '0';
    end if;
    if SHCLK'EVENT and SHCLK= '1'and BUSY='1' then
      ----2)Shift
      SO<=OREG(COUNT);
      COUNT := COUNT - 1;
      ----3)Shift Complete
      if COUNT < 0 then
        SH_COMP <= '1';
      end if;
    end if;
  end process SHIFT;
end TWO_PROC;
---Parallel to Serial Converter

entity BUFF_REG is
     generic(STRB_DEL,EN_DEL,ODEL: TIME);
     port(DI:  in BIT_VECTOR(1 to 8);
       STRB: in BIT;DS1:  in BIT;
       NDS2: in BIT;
       DO: out BIT_VECTOR(1 to 8));
  end BUFF_REG;
  --
  architecture THREE_PROC of BUFF_REG is
     signal REG: BIT_VECTOR(1 to 8);
     signal ENBLD: BIT;
  begin
  PREG: process(STRB)
     begin
        if (STRB = '1') then
           REG <=DI after STRB_DEL;
        end if;
  end process PREG;
  --
  ENABLE: process(DS1,NDS2)
     begin
        ENBLD <= DS1 and  not NDS2 after EN_DEL;
  end process ENABLE;
  --
  OUTPUT: process(REG,ENBLD)
     begin
        if (ENBLD = '1')
        then
           DO <= REG after ODEL;
        else
           DO <= "11111111" after ODEL;
        end if;
  end process OUTPUT;
  end THREE_PROC;
--Figure 5.9 Algorithmic VHDL description for buffered register.