---------------------------------------------------------
--Primitive name: ORGATE
--Purpose: An OR gate for multiple value logic STD_LOGIC,
-- N inputs, 1 output.
--(see package IEEE.STD_LOGIC_1164 for truth table)
---------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_MISC.all;
entity ORGATE is
  generic (N:   Positive := 2;-- number of inputs
           tLH: Time := 0 ns; -- rise inertial delay
           tHL: Time := 0 ns; -- fall inertial delay
           STRN: STRENGTH := STRN_X01);-- output strength
  port (INPUT: in STD_LOGIC_VECTOR (1 to N);-- inputs
        OUTPUT: out STD_LOGIC);  -- output
end ORGATE;

architecture A of ORGATE is
  signal CURRENTSTATE: STD_LOGIC := 'U';
  subtype TWOBIT is STD_LOGIC_VECTOR (0 to 1);
begin
  P: process
    variable NEXTSTATE: STD_LOGIC;
    variable DELTA: Time;
    variable NEXT_ASSIGN_VAL: STD_LOGIC;
  begin
  -- evaluate logical function
    NEXTSTATE := '0';
    for i in INPUT'range loop
      NEXTSTATE := INPUT(i) or NEXTSTATE;
      exit when NEXTSTATE = '1';
    end loop;
    NEXTSTATE := STRENGTH_MAP(NEXTSTATE, STRN);
    if (NEXTSTATE /= NEXT_ASSIGN_VAL) then
    -- compute delay
      case TWOBIT'(CURRENTSTATE & NEXTSTATE) is
        when "UU"|"UX"|"UZ"|"UW"|"U-"|"XU"|"XX"|"XZ"|"XW"|
             "X-"|"ZU"|"ZX"|"ZZ"|"ZW"|"Z-"|"WU"|"WX"|"WZ"|
             "WW"|"W-"|"-U"|"-X"|"-Z"|"-W"|"--"|"00"|"0L"|
             "LL"|"L0"|"11"|"1H"|"HH"|"H1"
          => DELTA := 0 ns;
        when "U1"|"UH"|"X1"|"XH"|"Z1"|"ZH"|"W1"|"WH"|"-1"|
             "-H"|"0U"|"0X"|"01"|"0Z"|"0W"|"0H"|"0-"|"LU"|
             "LX"|"L1"|"LZ"|"LW"|"LH"|"L-"
          => DELTA := tLH;
        when others => DELTA := tHL;
      end case;
    -- assign new value after internal delay
      CURRENTSTATE <= NEXTSTATE after DELTA;
      OUTPUT <= NEXTSTATE after DELTA;
      NEXT_ASSIGN_VAL := NEXTSTATE;
    end if;
  -- wait for signal changes
    wait on INPUT;
  end process P;
end A;
--Figure 7.34 OR gate model