#         (C) Copyright 1991 - 1997 Exemplar Logic, Inc.  All Rights Reserved.
#
#
#                                      NOTICE
#
#          This file belongs to Exemplar Logic, Inc.  It is
#          considered trade secret and is not to be divulged or used by
#          parties who have not received written authorization from
#          the owner.
#
############ Project Settings ############
set process "2"
set part "EPF10K70RC240"
set tristate_map "FALSE"
set opt_best_result "33.660000"
set opt_best_pass "1"
set input2register "20.000000"
set register2output "20.000000"
set register2register "20.000000"
set encoding "auto"
set edifin_ground_port_names "GND"
set edifin_power_port_names "VCC"
set edif_function_property "lut_function"
set edif_array_range_extraction_style "%s\[%d:%d\]"
set edif_eqn_or "+"
set edif_eqn_and " "
set edif_eqn_not "'"
set edif_eqn_not_is_prefix "FALSE"
set modgen_select "auto"
set optimize_timing_cpu_limit "0"

if ![is_var_set dont_restore_design] {
###### Loading technology libraries #######
    load_library flex10
}