-- file name: rtl_pack.vhd
-- purpose: define the basic components (half_adder, full_adder, sum12_pp,
-- 					 full_substractor, sum12_pm, reg1,reg3, 
--					 reg8, reg12, mux1_by2, Mux12_by_2, 
--					 abs12,reg_angle, compare_GE)
 				 

--------------------------------------------------------------------------------

-- **************
-- * Half_Adder *
-- **************
library IEEE;
use IEEE.std_logic_1164.all;
  
entity Half_Adder is
    port(
      A, B    : in std_logic:='0';
      Y, Cout : out std_logic:='0'
   );
end Half_Adder;

architecture DataFlow of Half_Adder is
begin
   Y    <=  A xor B;
   Cout <=  A and B;
end DataFlow;

-----------------------------------------------------------------------------

-- **************
-- * Full_Adder *
-- **************

library IEEE;
use ieee.std_logic_1164.all;
   
entity Full_Adder is
    port(A, B, Cin : in std_logic:='0';
        Sum, Cout : out std_logic:='0');
end Full_Adder;

architecture DataFlow of Full_Adder is

begin
   
   Sum  <= A xor B xor Cin;
   Cout <= (A and B) or (A and Cin) or (B and Cin);

end DataFlow;

 -----------------------------------------------------------------------------

-- *********************
-- * 12-bit Full_Adder *
-- *********************

library IEEE;
use ieee.std_logic_1164.all;
  
library STRUC_RTL;
use STRUC_RTL.all;

entity Sum12_PP is
   
   port(Arg1   : in std_logic_vector(11 downto 0):="000000000000";
        Arg2   : in std_logic_vector(11 downto 0):="000000000000";
        Result : out std_logic_vector(11 downto 0):="000000000000");

end Sum12_PP;
 
architecture Parts of Sum12_PP is

   component Full_Adder
     port(A, B, Cin : in std_logic:='0';
        Sum, Cout : out std_logic:='0');
   end component;

   for all : Full_Adder use entity STRUC_RTL.Full_Adder(DataFlow);

   signal C0, C1, C2, C3, C4, C5, C6, C7, 
          C8, C9, C10, C11, C12 :std_logic:='0';
begin
   C0 <= '0';
   Fa0  : Full_Adder port map( Arg1( 0), Arg2( 0), C0,  Result( 0), C1 );
   Fa1  : Full_Adder port map( Arg1( 1), Arg2( 1), C1,  Result( 1), C2 );
   Fa2  : Full_Adder port map( Arg1( 2), Arg2( 2), C2,  Result( 2), C3 );
   Fa3  : Full_Adder port map( Arg1( 3), Arg2( 3), C3,  Result( 3), C4 );
   Fa4  : Full_Adder port map( Arg1( 4), Arg2( 4), C4,  Result( 4), C5 );
   Fa5  : Full_Adder port map( Arg1( 5), Arg2( 5), C5,  Result( 5), C6 );
   Fa6  : Full_Adder port map( Arg1( 6), Arg2( 6), C6,  Result( 6), C7 );
   Fa7  : Full_Adder port map( Arg1( 7), Arg2( 7), C7,  Result( 7), C8 );
   Fa8  : Full_Adder port map( Arg1( 8), Arg2( 8), C8,  Result( 8), C9 );
   Fa9  : Full_Adder port map( Arg1( 9), Arg2( 9), C9,  Result( 9), C10);
   Fa10 : Full_Adder port map( Arg1(10), Arg2(10), C10, Result(10), C11);
   Fa11 : Full_Adder port map( Arg1(11), Arg2(11), C11, Result(11), C12);

end Parts;
-----------------------------------------------------------------------------

-- ******************* 
-- * Full_Subtractor *
-- ******************* 

library IEEE;
use ieee.std_logic_1164.all;
  
entity Full_Subtractor is
   port(A, B, Bin : in std_logic:='0';
        Diff, Bout: out std_logic:='0');
end Full_Subtractor;

architecture DataFlow of Full_Subtractor is
 
begin
  
   Diff  <= A xor B xor Bin;
   Bout  <= (not(A) and B) or (B and Bin) or (not(A) and Bin);

end DataFlow;

------------------------------------------------------------------------------

-- **************************
-- * 12-bit Full_Subtractor *
-- **************************

library IEEE;
use ieee.std_logic_1164.all;
  
library STRUC_RTL;
use STRUC_RTL.all;
 
entity Sum12_PM is
   port(Arg1   : in std_logic_vector(11 downto 0):="000000000000";
        Arg2   : in std_logic_vector(11 downto 0):="000000000000";
        Result : out std_logic_vector(11 downto 0):="000000000000");
end Sum12_PM;

architecture Parts of Sum12_PM is

   component Full_Subtractor
      port(A, B, Bin : in std_logic:='0';
        Diff, Bout   : out std_logic:='0');
   end component;
for all : Full_Subtractor use entity STRUC_RTL.Full_Subtractor(DataFlow);

   signal C0, C1, C2, C3, C4, C5, C6, 
          C7, C8, C9, C10, C11, C12 : std_logic:='0';
begin
   C0 <= '0';
   Fs0  : Full_Subtractor port map( Arg1( 0), Arg2( 0), C0,  Result( 0), C1 );
   Fs1  : Full_Subtractor port map( Arg1( 1), Arg2( 1), C1,  Result( 1), C2 );
   Fs2  : Full_Subtractor port map( Arg1( 2), Arg2( 2), C2,  Result( 2), C3 );
   Fs3  : Full_Subtractor port map( Arg1( 3), Arg2( 3), C3,  Result( 3), C4 );
   Fs4  : Full_Subtractor port map( Arg1( 4), Arg2( 4), C4,  Result( 4), C5 );
   Fs5  : Full_Subtractor port map( Arg1( 5), Arg2( 5), C5,  Result( 5), C6 );
   Fs6  : Full_Subtractor port map( Arg1( 6), Arg2( 6), C6,  Result( 6), C7 );
   Fs7  : Full_Subtractor port map( Arg1( 7), Arg2( 7), C7,  Result( 7), C8 );
   Fs8  : Full_Subtractor port map( Arg1( 8), Arg2( 8), C8,  Result( 8), C9 );
   Fs9  : Full_Subtractor port map( Arg1( 9), Arg2( 9), C9,  Result( 9), C10);
   Fs10 : Full_Subtractor port map( Arg1(10), Arg2(10), C10, Result(10), C11);
   Fs11 : Full_Subtractor port map( Arg1(11), Arg2(11), C11, Result(11), C12);
end Parts;

--------------------------------------------------------------------------------

-- ******************
-- * 1-bit register *
-- ******************

library IEEE;
use ieee.std_logic_1164.all;
  
entity Reg1 is
    generic(reg_delay:time);
    port(
      Input  : in std_logic:='0';
      Output : out std_logic:='0';
      Strobe : in std_logic:='0'   
   );
end Reg1;

architecture Behave of Reg1 is
begin
   process(Strobe)
   begin

   if Strobe'event and Strobe='1' then
      Output <= Input;-- after reg_delay;
   end if;
   end process;
end Behave;

--------------------------------------------------------------------------------

-- ******************
-- * 3-bit register *
-- ******************

library IEEE;
use ieee.std_logic_1164.all; 
 
library STRUC_RTL;
use STRUC_RTL.all;

entity Reg3 is
    generic(angle_delay:time);
    port(Inputs  : in std_logic_vector(2 downto 0):="000";
        Outputs : out std_logic_vector(2 downto 0):="000";
        Strobe  : in std_logic:='0');
end Reg3;

architecture parts of Reg3 is

component  Reg1
    generic(reg_delay:time);
    port(Input  : in std_logic:='0';
        Output : out std_logic:='0';
        Strobe : in std_logic:='0');
end component;

for all :  Reg1 use entity STRUC_RTL.Reg1(Behave);


begin

RA_1 :  Reg1 generic map(angle_delay) 
        port map(inputs(0),outputs(0),strobe);
RA_2 :  Reg1 generic map(angle_delay) 
	port map(inputs(1),outputs(1),strobe);
RA_3 :  Reg1 generic map(angle_delay) 
	port map(inputs(2),outputs(2),strobe);

end parts;

--------------------------------------------------------------------------------

-- ******************
-- * 8-bit register *
-- ******************

library IEEE;
use ieee.std_logic_1164.all;
  
library STRUC_RTL;
use STRUC_RTL.all;
 
entity Reg8 is
    generic(reg_delay:time);
    port(Inputs  : in std_logic_vector(7 downto 0):="00000000";
        Outputs : out std_logic_vector(7 downto 0):="00000000";
        Strobe  : in std_logic:='0');
end Reg8;

architecture parts of Reg8 is

component  Reg1
    generic(reg_delay:time);
    port(
      Input  : in std_logic:='0';
      Output : out std_logic:='0';
      Strobe : in std_logic:='0'   
   );
end component;

for all :  Reg1 use entity STRUC_RTL.Reg1(Behave);


begin

R8_1 :  Reg1 generic map(reg_delay) 
	port map(inputs(0),outputs(0),strobe);
R8_2 :  Reg1 generic map(reg_delay)  
	port map(inputs(1),outputs(1),strobe);
R8_3 :  Reg1 generic map(reg_delay)  
	port map(inputs(2),outputs(2),strobe);
R8_4 :  Reg1 generic map(reg_delay)  
	port map(inputs(3),outputs(3),strobe);
R8_5 :  Reg1 generic map(reg_delay)  
	port map(inputs(4),outputs(4),strobe);
R8_6 :  Reg1 generic map(reg_delay)  
	port map(inputs(5),outputs(5),strobe);
R8_7 :  Reg1 generic map(reg_delay)  
	port map(inputs(6),outputs(6),strobe);
R8_8 :  Reg1 generic map(reg_delay)  
	port map(inputs(7),outputs(7),strobe);

end parts;
-------------------------------------------------------------------------------

-- *******************
-- * 12-bit register *
-- *******************

library IEEE;
use ieee.std_logic_1164.all;
   
library STRUC_RTL;
use STRUC_RTL.all;

entity Reg12 is
     generic(reg_delay:time);
     port(Inputs  : in std_logic_vector(11 downto 0):="000000000000";
        Outputs : out std_logic_vector(11 downto 0):="000000000000";
        Strobe  : in std_logic:='0');
end Reg12;

architecture parts of Reg12 is

component  Reg1
     generic(reg_delay:time);
       port(
      Input  : in std_logic:='0';
      Output : out std_logic:='0';
      Strobe : in std_logic:='0'   
   );
end component;

for all :  Reg1 use entity STRUC_RTL.Reg1(Behave);


begin
R12_1 : Reg1 generic map(reg_delay)  
	port map(inputs(0),outputs(0),strobe);
R12_2 : Reg1 generic map(reg_delay)  
	port map(inputs(1),outputs(1),strobe);
R12_3 : Reg1 generic map(reg_delay)  
	port map(inputs(2),outputs(2),strobe);
R12_4 : Reg1 generic map(reg_delay)  
	port map(inputs(3),outputs(3),strobe);
R12_5 : Reg1 generic map(reg_delay)  
	port map(inputs(4),outputs(4),strobe);
R12_6 : Reg1 generic map(reg_delay)  
	port map(inputs(5),outputs(5),strobe);
R12_7 : Reg1 generic map(reg_delay)  
	port map(inputs(6),outputs(6),strobe);
R12_8 : Reg1 generic map(reg_delay)  
	port map(inputs(7),outputs(7),strobe);
R12_9 : Reg1 generic map(reg_delay)  
	port map(inputs(8),outputs(8),strobe);
R12_10 :Reg1 generic map(reg_delay) 
	port map(inputs(9),outputs(9),strobe);
R12_11 :Reg1 generic map(reg_delay)  
	port map(inputs(10),outputs(10),strobe);
R12_12 :Reg1 generic map(reg_delay)  
	port map(inputs(11),outputs(11),strobe);

end parts;

--------------------------------------------------------------------------------

-- ****************************
-- * 1-bit 2-to-1 Multiplexer *
-- ****************************

library IEEE;
use ieee.std_logic_1164.all;
   
entity Mux1_by_2 is
   port(
      A, B     : in std_logic:='0';
      Result   : out std_logic:='0';
      Select_B : in std_logic:='0'    
   );
end Mux1_by_2;

architecture Behave of Mux1_by_2 is
begin
   process( A, B, Select_B )
   begin
      if (Select_B = '1') then
	 Result <= B;
      elsif (Select_B = '0') then
	 Result <= A;
      else
	 Result <= 'U';
      end if;
   end process;
end Behave;

--------------------------------------------------------------------------------

-- ****************************
-- * 8-bit 2-to-1 Multiplexer *
-- ****************************

library IEEE;
use ieee.std_logic_1164.all;
   
library STRUC_RTL;
use STRUC_RTL.all;

entity Mux8_by_2 is
   port(
      A, B     : in std_logic_vector(7 downto 0):="00000000";  
      Result   : out std_logic_vector(7 downto 0):="00000000";
      Select_B : in std_logic:='0'     
   );
end Mux8_by_2;

architecture parts of Mux8_by_2 is

component  Mux1_by_2 
 port(A, B     : in std_logic:='0';
      Result   : out std_logic:='0';
      Select_B : in std_logic:='0');
end component;

for all:  Mux1_by_2 use entity STRUC_RTL.Mux1_by_2(Behave);

begin

M8_1:  Mux1_by_2 port map(A(0),B(0),Result(0),Select_B);
M8_2:  Mux1_by_2 port map(A(1),B(1),Result(1),Select_B);
M8_3:  Mux1_by_2 port map(A(2),B(2),Result(2),Select_B);
M8_4:  Mux1_by_2 port map(A(3),B(3),Result(3),Select_B);
M8_5:  Mux1_by_2 port map(A(4),B(4),Result(4),Select_B);
M8_6:  Mux1_by_2 port map(A(5),B(5),Result(5),Select_B);
M8_7:  Mux1_by_2 port map(A(6),B(6),Result(6),Select_B);
M8_8:  Mux1_by_2 port map(A(7),B(7),Result(7),Select_B);
 
end parts;

--------------------------------------------------------------------------------

-- *****************************
-- * 12-bit 2-to-1 Multiplexer *
-- *****************************

library IEEE;
use ieee.std_logic_1164.all;
   
library STRUC_RTL;
use STRUC_RTL.all;

entity Mux12_by_2 is
   port(
      A, B     : in std_logic_vector(11 downto 0):="000000000000";  
      Result   : out std_logic_vector(11 downto 0):="000000000000";
      Select_B : in std_logic:='0'     
   );
end Mux12_by_2;

architecture parts of Mux12_by_2 is

component  Mux1_by_2 
 port(A, B     : in std_logic:='0';
      Result   : out std_logic:='0';
      Select_B : in std_logic:='0');
end component;

for all:  Mux1_by_2 use entity STRUC_RTL.Mux1_by_2(Behave);

begin

M12_1:  Mux1_by_2 port map(A(0),B(0),Result(0),Select_B);
M12_2:  Mux1_by_2 port map(A(1),B(1),Result(1),Select_B);
M12_3:  Mux1_by_2 port map(A(2),B(2),Result(2),Select_B);
M12_4:  Mux1_by_2 port map(A(3),B(3),Result(3),Select_B);
M12_5:  Mux1_by_2 port map(A(4),B(4),Result(4),Select_B);
M12_6:  Mux1_by_2 port map(A(5),B(5),Result(5),Select_B);
M12_7:  Mux1_by_2 port map(A(6),B(6),Result(6),Select_B);
M12_8:  Mux1_by_2 port map(A(7),B(7),Result(7),Select_B);
M12_9:  Mux1_by_2 port map(A(8),B(8),Result(8),Select_B);
M12_10:  Mux1_by_2 port map(A(9),B(9),Result(9),Select_B);
M12_11:  Mux1_by_2 port map(A(10),B(10),Result(10),Select_B);
M12_12:  Mux1_by_2 port map(A(11),B(11),Result(11),Select_B);

end parts;

--------------------------------------------------------------------------------

-- ********************
-- * 12-bit absoluter *
-- ********************

library IEEE;
use ieee.std_logic_1164.all;
  
library STRUC_RTL;
use STRUC_RTL.all;

entity Abs12 is
   port(
      A : in std_logic_vector(11 downto 0):="000000000000";   
      Y : out std_logic_vector(11 downto 0):="000000000000"
      );
end Abs12;

architecture Parts of Abs12 is

component  Mux12_by_2
      port (A, B     : in std_logic_vector(11 downto 0):="000000000000"; 
            Result   : out std_logic_vector(11 downto 0):="000000000000"; 
           Select_B : in std_logic:='0');
end component;

component  Half_Adder
      port (A, B    : in std_logic:='0';
         Y, Cout : out std_logic:='0');
end component;

for all :  Mux12_by_2 use entity STRUC_RTL.Mux12_by_2(Parts);
for all :  Half_Adder use entity STRUC_RTL.Half_Adder(DataFlow);

signal OneComp : std_logic_vector(11 downto 0):="000000000000";
signal C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12:std_logic:='0';
signal TwoComp : std_logic_vector(11 downto 0):="000000000000";

begin
   OneComp( 0) <= Not( A( 0) );
   OneComp( 1) <= Not( A( 1) );
   OneComp( 2) <= Not( A( 2) );
   OneComp( 3) <= Not( A( 3) );
   OneComp( 4) <= Not( A( 4) );
   OneComp( 5) <= Not( A( 5) );
   OneComp( 6) <= Not( A( 6) );
   OneComp( 7) <= Not( A( 7) );
   OneComp( 8) <= Not( A( 8) );
   OneComp( 9) <= Not( A( 9) );
   OneComp(10) <= Not( A(10) );
   OneComp(11) <= Not( A(11) );

   -- add 1
   C0 <= '1';
   H0  :  Half_Adder port map( OneComp( 0), C0,  TwoComp( 0), C1 );
   H1  :  Half_Adder port map( OneComp( 1), C1,  TwoComp( 1), C2 );
   H2  :  Half_Adder port map( OneComp( 2), C2,  TwoComp( 2), C3 );
   H3  :  Half_Adder port map( OneComp( 3), C3,  TwoComp( 3), C4 );
   H4  :  Half_Adder port map( OneComp( 4), C4,  TwoComp( 4), C5 );
   H5  :  Half_Adder port map( OneComp( 5), C5,  TwoComp( 5), C6 );
   H6  :  Half_Adder port map( OneComp( 6), C6,  TwoComp( 6), C7 );
   H7  :  Half_Adder port map( OneComp( 7), C7,  TwoComp( 7), C8 );
   H8  :  Half_Adder port map( OneComp( 8), C8,  TwoComp( 8), C9 );
   H9  :  Half_Adder port map( OneComp( 9), C9,  TwoComp( 9), C10 );
   H10 :  Half_Adder port map( OneComp(10), C10, TwoComp(10), C11 );
   H11 :  Half_Adder port map( OneComp(11), C11, TwoComp(11), C12 );

   Mux :  Mux12_by_2 port map( A, TwoComp, Y, A(11) );

end Parts;

--------------------------------------------------------------------------------

-- *********************
-- * 12-bit Comparator *
-- *********************

library IEEE;
use ieee.std_logic_1164.all;
  
library STRUC_RTL;
use STRUC_RTL.all;

entity Compare_GE is
   port(A, B : in std_logic_vector(11 downto 0):="000000000000";
        A_GreaterEqual_B : out std_logic:='0');
end Compare_GE;

architecture Parts of Compare_GE is

component Full_Subtractor
   port(A, B, Bin : in std_logic:='0';
        Diff, Bout: out std_logic:='0');
end component;

for all : Full_Subtractor use entity STRUC_RTL.Full_Subtractor(DataFlow);

signal C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12:std_logic:='0';
signal Result : std_logic_vector(11 downto 0):="000000000000";

begin
   C0 <= '0';
   Fs0  : Full_Subtractor port map( A( 0), B( 0), C0,  Result( 0), C1  );
   Fs1  : Full_Subtractor port map( A( 1), B( 1), C1,  Result( 1), C2  );
   Fs2  : Full_Subtractor port map( A( 2), B( 2), C2,  Result( 2), C3  );
   Fs3  : Full_Subtractor port map( A( 3), B( 3), C3,  Result( 3), C4  );
   Fs4  : Full_Subtractor port map( A( 4), B( 4), C4,  Result( 4), C5  );
   Fs5  : Full_Subtractor port map( A( 5), B( 5), C5,  Result( 5), C6  );
   Fs6  : Full_Subtractor port map( A( 6), B( 6), C6,  Result( 6), C7  );
   Fs7  : Full_Subtractor port map( A( 7), B( 7), C7,  Result( 7), C8  );
   Fs8  : Full_Subtractor port map( A( 8), B( 8), C8,  Result( 8), C9  );
   Fs9  : Full_Subtractor port map( A( 9), B( 9), C9,  Result( 9), C10 );
   Fs10 : Full_Subtractor port map( A(10), B(10), C10, Result(10), C11 );
   Fs11 : Full_Subtractor port map( A(11), B(11), C11, Result(11), C12 );

   A_GreaterEqual_B <= not( C12 );

end Parts;

 
library IEEE;
use IEEE.std_logic_1164.all;
  
entity decoder is
    generic(decoder_delay:time);
    port(Input: in std_logic_vector(1 downto 0);
       	 D3,D2,D1,D0 : 	out std_logic:='0');
end decoder;

architecture behavior of decoder is
begin
  process(Input)
        begin
 	case  Input is
	when "00" => D3 <= '0' after decoder_delay;
		     D2 <= '0' after decoder_delay;
		     D1 <= '0' after decoder_delay;
		     D0 <= '1' after decoder_delay;

	when "01" => D3 <= '0' after decoder_delay;
		     D2 <= '0' after decoder_delay;
		     D1 <= '1' after decoder_delay;
		     D0 <= '0' after decoder_delay;

	when "10" => D3 <= '0' after decoder_delay;
		     D2 <= '1' after decoder_delay;
		     D1 <= '0' after decoder_delay;
		     D0 <= '0' after decoder_delay;

	when "11"  =>D3 <= '1' after decoder_delay;
		     D2 <= '0' after decoder_delay;
		     D1 <= '0' after decoder_delay;
		     D0 <= '0' after decoder_delay;
        when others => Null;
        end case;
  end process;
end behavior;


library IEEE;
use IEEE.std_logic_1164.all;
  
entity And2 is
    generic(and_delay:time);
    port(I0,I1: in std_logic:='0';
       	 O : 	out std_logic:='0');
end And2;

architecture behavior of And2 is
begin
	O <= I0 and I1 after and_delay;
end behavior;


library IEEE;
use IEEE.std_logic_1164.all;
  
entity Or2 is
    generic(or_delay:time);
    port(I0,I1: in std_logic:='0';
       	 O : 	out std_logic:='0');
end Or2;

architecture behavior of Or2 is
begin
	O <= I0 or I1 after or_delay;
end behavior;


library IEEE;
use ieee.std_logic_1164.all;

entity buff is
	generic(buff_delay:time);
 	port(INPUT: in std_logic;
	     ENABLE: in std_logic;
	     OUTPUT: out std_logic);
end buff;

architecture behavior of buff is
begin
  process(ENABLE,INPUT)
  begin
       	if ENABLE ='1' then
	  OUTPUT <= INPUT after buff_delay; 
	end if;
        if ENABLE = '0' then
	  OUTPUT <= 'Z' after buff_delay;
	end if;
  end process;
end behavior;
	
library STRUC_RTL;
use STRUC_RTL.image_processing.all;

library IEEE;
use ieee.std_logic_1164.all;

entity buff8 is
	generic(buff_delay:time);
  	port(INPUT: in pixel;
	     ENABLE: in std_logic;
	     OUTPUT: out pixel);
end buff8;

architecture structure of buff8 is
component buffa
	generic(buff_delay:time);
 	port(INPUT: in std_logic;
	     ENABLE: in std_logic;
	     OUTPUT: out std_logic);
end component;
for all: buffa use entity struc_rtl.buff(behavior);
signal one:std_logic:='1';
begin
p1: buffa
generic map(buff_delay)
port map(input(7),enable,output(7));
p2: buffa
generic map(buff_delay)
port map(input(6),enable,output(6));
p3: buffa
generic map(buff_delay)
port map(input(5),enable,output(5));
p4: buffa
generic map(buff_delay)
port map(input(4),enable,output(4));
p5: buffa
generic map(buff_delay)
port map(input(3),enable,output(3));
p6: buffa
generic map(buff_delay)
port map(input(2),enable,output(2));
p7: buffa
generic map(buff_delay)
port map(input(1),enable,output(1));
p8: buffa
generic map(buff_delay)
port map(input(0),enable,output(0));

end structure;
	

library STRUC_RTL;
use STRUC_RTL.image_processing.all;

library IEEE;
use ieee.std_logic_1164.all;

entity FOUR_TO_ONE_MUX is 
    generic(mux_delay:time);
    port(IN0,IN1,IN2,IN3: in pixel;
         S : in std_logic_vector(1 downto 0);
         O : out pixel);
end FOUR_TO_ONE_MUX;

architecture behavior of FOUR_TO_ONE_MUX is 
begin
  process(S,IN0,IN1,IN2,IN3)
    begin
	case S is
		when "00" => O <= IN0 after mux_delay;
		when "01" => O <= IN1 after mux_delay;
		when "10" => O <= IN2 after mux_delay;
		when "11" => O <= IN3 after mux_delay;
		when others => O <= "ZZZZZZZZ" after mux_delay;
	end case;
    end process;
end behavior;

library IEEE;
use ieee.std_logic_1164.all;

entity not_gate is
  generic(not_delay:time);
  port(I: in std_logic;
       O: out std_logic);
end not_gate;

architecture behavior of not_gate is
begin
  O <= not(I) after not_delay;
end behavior;