library ieee;
use ieee.std_logic_1164.all;

entity CLOCK_DIV is
  port (CLK, RESET : in std_logic;
        CLK_OUT: out std_logic);
end CLOCK_DIV;

architecture SYNTH of CLOCK_DIV is
  signal CLK_T1S : std_logic;
begin
  process(CLK, RESET)
    variable COUNT : integer range 0 to 5000000;
  begin
    if (RESET = '1') then
      COUNT := 0;
      CLK_T1S <= '0';
    elsif (CLK'event and CLK = '1') then
      if (COUNT = 5000000) then
        COUNT := 0;
        CLK_T1S <= not CLK_T1S;
      else
        COUNT := COUNT + 1;
      end if;
    end if;
  end process;
  CLK_OUT <= CLK_T1S;
end SYNTH;