library ieee;
use ieee.std_logic_1164.all;
--use work.all;

entity CLOCK_TEST is
end CLOCK_TEST;

architecture TEST of CLOCK_TEST is
  signal CLOCK : std_logic := '0';
  signal RESET, CLOCK_1S : std_logic;
begin
  U1: entity work.CLOCK_DIV(SYNTH)
    port map (CLOCK, RESET, CLOCK_1S);
  process(CLOCK)
  begin
    CLOCK <= not CLOCK after 50 ns;
  end process;
  process
  begin
    RESET <= '1' after 5 ns, '0' after 75 ns;
    wait;
  end process;
end TEST;