use WORK.all;
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_arith.all;
use std.TEXTIO.all;

entity WASH_TEST_BENCH is
end WASH_TEST_BENCH;

library ieee;
use IEEE.std_logic_1164.all;

architecture TEST of WASH_TEST_BENCH is
  signal RESET, START, FULL, EMPTY : std_logic;
  signal HOT, COLD, DRAIN, TURN : std_logic;
  signal DIAL : std_logic_vector (5 downto 0);
  signal CLK : std_logic := '0';
begin
  U1: entity work.WASH(STRUCTURE)
      port map (CLK, RESET, START, FULL, EMPTY,
                DIAL, HOT, COLD, DRAIN, TURN);
  process(CLK)
  begin
    CLK <= not CLK after 500 ms;
  end process;
  process
    variable VLINE: LINE;
    variable V1 : std_logic_vector (3 downto 0);
    variable V2 : integer;
    file INVECT : TEXT is "wash.txt";
  begin
    READLINE(INVECT, VLINE);
    READLINE(INVECT, VLINE);
    READ(VLINE, V1);
    RESET <= V1(3);
    START <= V1(2);
    FULL <= V1(1);
    EMPTY <= V1(0);
    READ(VLINE, V2);
    DIAL <= conv_std_logic_vector(V2, 6);
    while not(ENDFILE(INVECT)) loop
      wait until CLK = '0';
      READLINE(INVECT, VLINE);
      READ(VLINE, V1);
      RESET <= V1(3);
      START <= V1(2);
      FULL <= V1(1);
      EMPTY <= V1(0);
      READ(VLINE, V2);
      DIAL <= conv_std_logic_vector(V2, 6);
      wait until CLK = '1';
    end loop;
    wait;
  end process;
end TEST;