library ieee;
use ieee.std_logic_1164.all;

entity WASH is
  port (CK, RESET, START, FULL, EMPTY  : in std_logic;
        DIAL : in integer range 0 to 60;
        HOT, COLD, DRAIN, TURN : out std_logic);
end WASH;

architecture STRUCT of WASH is
  signal LOAD, DEC, ZERO, RESET_MINUTE : std_logic;
  signal COUNT : integer range 0 to 60;
begin
  U1: entity work.STATE_MACHINE(SYNTH)
        port map(CLK => CK, START => START, RESET => RESET,
                 FULL => FULL, EMPTY => EMPTY, ZERO => ZERO,
                 LOAD => LOAD, COUNT => COUNT, HOT => HOT,
                 COLD => COLD, DRAIN => DRAIN,
                 TURN => TURN, DIAL => DIAL);
  U2 : entity work.COUNT_DOWN(SYNTH)
         port map(LOAD => LOAD, DEC => DEC, CLK => CK, 
                  ZERO => ZERO, COUNT => COUNT,
                  RESET => RESET, RESET_MINUTE => RESET_MINUTE);
  U3 : entity work.COUNT_MINUTE(SYNTH)
         port map(RESET => RESET_MINUTE, CLK => CK, ZERO => DEC);
end STRUCT;