uah_bar

 

Department of Electrical and Computer Engineering

 

CPE/EE427, CPE527 VLSI Design I

(Section 01, MW 3:55 – 5:15pm, EB219)

Fall 2008

 

 

Instructor Contact

 

Instructor:                  Joel Wilder

Email:                         joel dot wilder at us dot army dot mil

Office:                        EB219

Phone:                       (256) 876-5910

Office Hours:            MW 5:15 – 6:15pm

 

Lab Instructor:           Vignesh Subbian

Email:                         vs0002 at uah dot edu

Office:                        EB223

Office Hours:            W 2:30 – 3:30pm

 

Course Information

 

Goals:            This course provides an introduction to digital integrated circuits.

A major course project allows students to apply principles learned during the class/lab and provides hands-on design experience.

 

Topics:          CMOS devices and manufacturing technology

CMOS inverters and gates

Propagation delay, noise margins, and power dissipation

Sequential circuits, arithmetic, interconnect, array structures and memories

Design methodologies

 

Textbook:     Neil H. E. Weste, David Harris, CMOS VLSI Design:  A Circuits and System Perspective, Addison Wesley, 3rd edition, 2005, ISBN: 0-321-14901-7

 

References: J. Rabaey, A. Chandarakasan, B. Nikolic, Digital Integrated Circuits: A Design Perspective, Prentice Hall, 2nd edition, ISBN:  0-13-090996-3.
                        Book Web site: http://bwrc.eecs.berkeley.edu/IcBook/

 

Prerequisites: EE 202 Introduction to Digital Logic Design, EE 315 Introduction to Electronic Analysis and Design

 

Syllabus:      here

 

Grading Policy:       Lab assignments – 15%

                                    Homeworks – 15%

                                    Test I – 20%

                                    Test II – 20%

                                    Project – 25%

                                    Discretion – 5%

 

 

Announcements

 

Remember to communicate with your instructor!

General announcement area for class communication.

 

Course Outline

 

 

Class

Date

Lecture

Additional Notes

1

8/18/2008

Introduction, Design Metrics

 

2

8/20/2008

IC Fabrication

 

3

8/25/2008

IC Fabrication and Design Rules

 

4

8/27/2008

MOS Transistor Theory

 

5

9/1/2008

None

Labor Day Holiday

6

9/3/2008

CMOS Inverter

 

7

9/8/2008

Static CMOS

 

8

9/10/2008

Static CMOS, Pass Logic

 

9

9/15/2008

Pass Logic

 

 10

9/17/2008

Delay Estimation

 

11

9/22/2008

Logical Effort

 

12

9/24/2008

Logical Effort

 

13

9/29/2008

Design for Speed

 

14

10/1/2008

Wires (Interconnect)

 

15

10/6/2008

Review for Test I

 

16

10/8/2008

None

TEST I

17

10/13/2008

Power, Design for Power

 

18

10/15/2008

Power, Design for Power

 

19

10/20/2008

Verilog Tutorial I, Verilog Tutorial II

 

20

10/22/2008

Circuit Families

 

21

10/27/2008

Circuit Families

 

22

10/29/2008

Circuit Families

 

23

11/3/2008

Sequential Circuits

 

24

11/5/2008

Sequential Circuits

 

25

11/10/2008

Project work session

 

26

11/12/2008

Review for Test II

 

27

11/17/2008

Project demonstrations

 

28

11/19/2008

Project presentations

 

29

11/24/2008

None

TEST II

 

Final Project due December 3, 3:00pm

 

Laboratory Assignments

 

The lab assignments serve two purposes.  First, they allow the students to apply what is taught during lectures.  Second, after completing all lab assignments, the students will have the skills required to complete the main purpose of the lab – the final project. During the first semester the students will design and verify a VLSI circuit using the Cadence tools.

 

Lab Session:  Tuesday, 7:00 – 8:30pm

 

Any required files that you might need for the labs are found here.

 

Lab Number

Issued

Due

Assignment

1

8/25/2008

9/2/2008

Lab #1

2

9/2/2008

9/16/2008

Lab #2

3

9/16/2008

9/23/2008

Lab #3

4

9/23/2008

10/7/2008

Lab #4

5

10/7/2008

10/21/2008

(see Vignesh)

 

 

Homework Assignments

 

Homework Number

Issued

Due

Assignment

1

9/3/2008

9/15/2008

HW #1

2

9/18/2008

10/1/2008

HW #2

3

10/28/2008

11/5/2008

HW #3

4

11/5/2008

11/17/2008

HW #4